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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev.? a 02/09/2012 ? is62/65WV2568DALL? is62/65wv2568dbll ? copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances 256k?x?8? low? voltage, ? ultra ? low? power?cmos? static?ram ? ? ?????? ????? ??? features ? high-speed access time: 35ns, 45ns, 55ns ? cmos low power operation C 36 mw (typical) operating C 9 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 1.8v 10% v cc (is62/65WV2568DALL) C 2.5vC3.6v v cc (is62/65wv2568dbll) ? fully static operation: no clock or refresh required ? three state outputs ? industrial temperature available ? lead-free available description the issi is62/65WV2568DALL and is62/65wv2568dbll are high-speed, 2m bit static rams organized as 256k words by 8 bits. it is fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) , the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. the is62/65WV2568DALL and is62/65wv2568dbll are packaged in the jedec standard 32-pin tsop (type i), stsop (type i), and 36-pin mini bga. functional?block? diagram february ?2012 a0-a17 cs1 oe we 256k x 8 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7 cs2
is62/65WV2568DALL, ??is62/65wv2568dbll? 2 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 pin?descriptions a0-a17 address inputs cs1 chip enable 1 input cs2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection vcc power gnd ground 36-pin?mini?bga?(b)??(6mm?x?8mm)? 32-pin? tsop?(type?i), ?stsop?(type?i)? pin? configuration 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd vcc i/o6 i/o7 a9 a1 a2 oe a10 cs2 we nc nc cs1 a11 a3 a4 a5 a17 a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 vcc gnd i/o2 i/o3 a14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we cs2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 3 rev.? a 02/09/2012 dc?electrical? characteristics? (over?operating? range) ? symbol? parameter ? test ?conditions? vcc? min. ? max. ? unit ? v oh output high voltage i oh = -0.1 ma 1.8v 10% 1.4 v i oh = -1 ma 2.5-3.6v 2.2 v v ol output low voltage i ol = 0.1 ma 1.8v 10% 0.2 v i ol = 2.1 ma 2.5-3.6v 0.4 v v ih input high voltage 1.8v 10% 1.4 v cc + 0.2 v 2.5-3.6v 2.2 v cc + 0.3 v v il (1) input low voltage 1.8v 10% C0.2 0.4 v 2.5-3.6v C0.2 0.6 v i li input leakage gnd v in v cc C1 1 a i lo output leakage gnd v out v cc , outputs disabled C1 1 a notes: for is62/65WV2568DALL: v il ( min.) = -1.0v a c (pluse width < 10ns). not 100% tested. v ih ( max.) = v cc + 1.0v a c ; ( pluse width < 10ns). not 100% tested. for is62/65wv2568dbll: v il ( min.) = -2.0v a c (pluse width < 10ns). not 100% tested. v ih ( max.) = v cc + 2.0v a c ; ( pluse width < 10ns). not 100% tested. absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit ? v term terminal voltage with respect to gnd C0.2 to vcc+0.3 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. operating ?range?(vcc) ? range ? ambient? temperature ? is62/65WV2568DALL ? is62/65wv2568dbll? ? commercial 0c to +70c 1.8v 10% 2.5v - 3.6v ? industrial C40c to +85c 1.8v 10% 2.5v - 3.6v automotive (a3) C40c to +125c 1.8v 10% 2.5v - 3.6v
is62/65WV2568DALL, ??is62/65wv2568dbll? 4 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 ac ? test? loads figure?1 figure?2 capacitance (1) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. ac ? test?conditions ? parameter ? 62wv2568dall ? 62wv2568dbll ? ? ? ? ? ? (unit)? (unit) ? input pulse level 0.4v to vcc-0.2v 0.4v to vcc-0.3v input rise and fall times 5 ns 5ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 ? ? 1.8v??10%?? 2.5v?-?3.6v ? r1(?) 3070 3070 r2 (?) 3150 3150 v ref 0.9v 1.5v v tm 1.8v 2.8v r1 30 pf including jig and scope r2 output vtm r1 5 pf including jig and scope r2 output vtm
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 5 rev.? a 02/09/2012 power ? supply? characteristics (1) ? (over operating range) ? symbol? parameter ? test ?conditions? ? max. ? max. ? max. ? unit ? ? ? ? ? 35ns? 45ns? 55ns i cc vcc dynamic operating v cc = max., com. 15 12 10 ma supply current i out = 0 ma, f = f max ind. 20 15 12 auto. 25 20 15 typ. (2) 10 8 6 i sb 1 ttl standby current v cc = max., com. 0.1 0.1 0.1 ma (ttl inputs) v in = v ih or v il ind. 0.1 0.1 0.1 cs1 = v ih , cs2 = v il , a uto . 0.2 0.2 0.2 f = 1 mh z ? i sb 2 cmos standby v cc = max., com. 7 7 7 a current (cmos inputs) cs1 v cc C 0.2v, ind. 10 10 10 cs2 0.2v, auto. C 18 18 v in v cc C 0.2v, or typ. (2) 3 v in 0.2v, f = 0 ? note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v cc = 3.0v, ta = 25 o c and not 100% tested.
is62/65WV2568DALL, ??is62/65wv2568dbll? 6 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 ac ? waveforms read?cycle? no. ?1 (1,2)? (address controlled) (cs1 = oe = v il , cs2 = we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address read?cycle?switching? characteristics (1) ? (over operating range) symbol parameter 35ns 45ns 55ns unit min. max. min. max. min. max. t rc read cycle time 35 45 55 ns t aa address access time 35 45 55 ns t oha output hold time 10 10 10 ns t a cs 1 /t a cs 2 cs1/cs2 access time 35 45 55 ns t doe oe access time 15 20 25 ns t hzoe (2) oe to high-z output 10 15 20 ns t lzoe (2) oe to low-z output 5 5 5 ns t hzcs 1 /t hzcs 2 (2) cs1/cs2 to high-z output 0 10 0 15 0 20 ns t lzcs 1 /t lzcs 2 (2) cs1/cs2 to low-z output 10 10 10 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 7 rev.? a 02/09/2012 ac ? waveforms read?cycle? no. ?2 (1,3) ( cs1, cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1= v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
is62/65WV2568DALL, ??is62/65wv2568dbll? 8 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 write?cycle?switching? characteristics (1,2) (over operating range) symbol parameter 35ns 45ns 55ns unit min. max. min. max. min. max. t wc write cycle time 35 45 55 ns t scs 1 /tscs 2 cs1/cs2 to write end 25 35 45 ns t aw address setup time to write end 25 35 45 ns t ha address hold from write end 0 0 0 ns t sa addrress setup time 0 0 0 ns t pwe we pulse width 30 35 40 ns t sd data setup to write end 15 20 25 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high-z output 20 20 20 ns t lzwe we high to low-z output 5 5 5 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. the internal write time is defned by the overlap of cs1 low, cs2 high and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac ? waveforms write?cycle? no. ?1?(cs1/cs2 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 9 rev.? a 02/09/2012 ac ? waveforms write?cycle? no. ?2? (we controlled: oe is high during write cycle) write?cycle? no. ?3? (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
is62/65WV2568DALL, ??is62/65wv2568dbll? 10 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 data ?retention?switching? characteristics ? ? symbol? parameter ? test ?condition? ? min. ? max. ? unit v dr vcc for data retention see data retention waveform 1.5 3.6 v i dr data retention current vcc = 1.5v, cs1 vcc C 0.2v, com. 7 a cs2 0.2v ind. 10 auto. 15 typ. (1) 2 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns data ?retention? waveform ?(cs1? controlled) data ?retention? waveform ?(cs2? controlled) v cc cs1 v cc - 0.2v t sdr t rdr v dr cs1 gnd 3.0v 2.2v data retention mode v cc cs2 0.2v t sdr t rdr v dr 0.4v cs2 gnd 3.0 2.2v data retention mode note: 1. typical values are measured at vcc = v dr (min), t a = 25 o c and not 100% tested.
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 11 rev.? a 02/09/2012 ordering? information is62wv2568dall ?(1.8??10%) industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? p ackage 55 is62wv2568dall-55ti tsop, type i 55 is62wv2568dall-55tli tsop, type i, lead-free 55 is62wv2568dall-55bi mini bga (6mm x 8mm) 55 is62wv2568dall-55bli mini bga (6mm x 8mm), lead-free 55 is62wv2568dall-55hi stsop, type i 55 is62wv2568dall-55hli stsop, type i, lead-free is62wv2568dbll?(2.5v?-?3.6v) industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? pac kage 35 is62wv2568dbll-35hli stsop, type i 35 is62wv2568dbll-35tli tsop, type i, lead-free 45 is62wv2568dbll-45ti tsop, type i 45 is62wv2568dbll-45tli tsop, type i, lead-free 45 is62wv2568dbll-45bi mini bga (6mm x 8mm) 45 is62wv2568dbll-45bli mini bga (6mm x 8mm), lead-free 45 is62wv2568dbll-45hi stsop, type i 45 is62wv2568dbll-45hli stsop, type i, lead-free is65wv2568dbll?(2.5v?-?3.6v) automotive ? range?(a3): ?C40c?to?+125c ? speed?(ns)? order ? part?no. ? pac kage 45 is65wv2568dbll-45tla3 tsop, type i, lead-free 45 is65wv2568dbll-45hla3 stsop, type i, lead-free
is62/65WV2568DALL, ??is62/65wv2568dbll? 12 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012
is62/65WV2568DALL, ??is62/65wv2568dbll? integrated silicon solution, inc. www.issi.com 13 rev.? a 02/09/2012
is62/65WV2568DALL, ??is62/65wv2568dbll? 14 integrated silicon solution, inc. www.issi.com rev.? a 02/09/2012 note : 1. controlling dimension : mm . 2. reference document : jedec mo-207 08/12/2008 package outline

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